The present invention is directed, in general, to integrated circuits and, more specifically, to an integrated circuit that includes copper metallization.
Copper metallization is used to form interconnects in integrated circuits. This has been done in the past by masking and etching a semiconductor substrate to form features such as damascene structures, windows, trenches and vias, then metallizing with tantalum (which is used as a barrier), forming a copper seed layer by physical vapor deposition (PVD) and then electro-chemically depositing (ECD) copper by electroless or electrolytic plating. The substrate is polished and the resulting copper-filled trenches are referred to as a xe2x80x9cdamascene structurexe2x80x9d, as one example. Unfortunately, this approach is known to form an undesirable grain structure in the copper, i.e., the copper grains grow from the walls of the features inward. It is preferred that the grain structure grows from the bottom of the feature upward. While not completely understood, it is suspected that orientation of the grain boundaries of the copper in a direction perpendicular to the flow of current is advantageous in that it may inhibit electromigration. Alternatively, a concomitant reduction in total grain boundary area may also be advantageous in reducing copper or point dislocation diffusion, thereby also inhibiting electromigration. In any case, it has recently been suggested that the application of titanium nitride to the tantalum prior to deposition of the copper will result in formation of such a desirable grain structure in the copper. However, titanium nitride provides poor conformal coverage inside features with aspect ratios greater than about 2:1 ( height, divided by diameter) thereby resulting in lack of copper fill-in in windows, vias or damascene structures and producing voids. Therefore, the creation of structures having higher aspect ratios would require repetition of the process suggested in the prior art in order to form xe2x80x9cdual damascenexe2x80x9d structures, which require an additional etch step to produce.
The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, and then forming copper over the titanium nitride, and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios. Use of this novel barrier improves electroplated copper interconnect reliability in integrated circuits. The invention may be used in all technologies with copper metallization.